Field of the Invention
The invention relates to a method for determining the power consumption of a programmable logic device, a method for designing a configuration of a programmable logic device, and a programming device for writing on a programmable logic device.
Description of the Background Art
In many technical fields, control units are used to control a physical process, wherein new measured values are acquired, preferably cyclically, from one or more sensors, and one or more actuators are driven on the basis of a comparison of the measured values with setpoint values. For rapid design of new control units and/or control algorithms, it is possible to build on an existing control unit and simply replace individual functions. As an alternative to this procedure, known as bypassing, it is also possible to connect a rapid control prototyping system (abbreviated as RCP system) that is specifically adapted for controller design in “full pass” operation to the sensors and actuators required for the desired control instead of a control unit. RCP systems are available that can also be used in the engine compartment of a motor vehicle because of their compact dimensions and passive cooling.
Programmable logic devices, known as Field Programmable Gate Arrays (FPGA), are increasingly being used for the simulation and control of highly dynamic systems. A programmable logic device comprises a plurality of logic elements and connecting elements as well as a clock supply that may comprise multiple clock regions. The logic elements include registers, truth tables (also known as lookup tables or LUT), adders, and delay units, for example. Frequency generators and dedicated computing devices, e.g. for multiplication, can also be present. The connecting elements usefully comprise conductive traces of differing lengths, which for example can also extend across regions of the FPGA, and switchable connections between the conductive traces and logic elements. After the power supply is switched on, the FPGA is initialized with a bit stream that usefully contains at least one bit for each logic element and for each switchable connecting element, and thus makes possible a circuit custom-tailored for the specific application. As a result of the good matching to the specific application and parallel processing of signals, FPGAs can also reliably control rapidly changing controlled systems, and are used to drive electronically commutated synchronous machines, for example.
A general problem in the use of programmable logic devices is that the dynamic power consumption of the FPGA depends heavily on the configuration, which is to say in particular the controller model being implemented, and on the stimuli, which is to say the signals present at the interface pins. Since changes at the interface pins can propagate through the entire FPGA and result in repeated switching of logic gates during a single clock, a high rate of change of the stimuli causes a significantly increased power consumption by the FPGA. When FPGAs are used in an RCP system, this can have critical consequences if the resultant waste heat overloads a passive cooling system or the power supply.
The article, “Dynamic Power Consumption in Virtex™-II FPGA Family,” by Li Shang et al., Proceedings of the ACM International Symposium on Field-Programmable Gate Arrays 2002, pp. 157-164, describes an analysis of the dynamic power consumption of a commercial FPGA that is substantially caused by charging and discharging of the capacitances of the individual elements of the programmable logic device and the short circuit currents during switching, for example, of inverters in the registers. It is proposed to determine the power consumption P using a formula P=½V2fΣiCiUiSi, where V is the supply voltage, f is the clock frequency, Ci is an effective capacitance, Ui is a utilization, and Si is a switching activity of the examined element i. The article also presents a possible procedure for estimating the power consumption based on a placed netlist of the configuration.
In U.S. Pat. No. 7,810,058 B1, a method for simulating operation of an integrated circuit is described in which an effective capacitance for the different types of programmable resources of the integrated circuit is determined before the device in question is manufactured. Based on a netlist, a switched capacitance for the specific type of programmable resource and a parasitic line capacitance are determined and combined. For each type, an average switching frequency is determined, and an estimated power consumption of the designed integrated circuit is determined on the basis thereof. In this way, a power consumption of an integrated circuit can be estimated at an early stage.
From U.S. Pat. No. 8,146,035 B1, a method is known for estimating the power consumption of a circuit based on a design for the circuit. A multiplicity of example circuit designs comprising circuit elements according to one or more structural templates is simulated in order to determine initial switching rates for the circuit elements, and a database of structural templates and associated equations that describe the initial switching rates is constructed. For a multiplicity of circuit elements from which the design for the circuit is constructed, a correspondence with the structural templates stored in the database is determined and an estimated switching rate is determined in each case based on the equations associated with the structural templates. Based on the estimated switching rates of the circuit elements, an estimated power consumption of the circuit is determined. This makes it possible to take into account structures having a switching frequency that differs significantly from the average when estimating the power consumption.
Manufacturers of programmable logic devices, such as Xilinx and Altera, often provide programs for estimating the power consumption of their FPGAs. While the manufacturers are well able to take into account the structural characteristics of the programmable logic device and the characteristics of the manufacturing process used, it is still the case that the dynamic behavior of a specific configuration can be described only with limited accuracy for reasons that include simplifying assumptions.